1. Technical Field
Example embodiments relate to a method of manufacturing a semiconductor device. More particularly, example embodiments relate to a method of manufacturing a semiconductor device including transistors having different conductive types.
2. Description of the Related Art
As information processing apparatuses are being widely used, semiconductor memory devices are being rapidly developed in response to this demand. Current semiconductor devices should have high response speed and large storage capacity. As a result, semiconductor manufacturing technology has been developed to provide a semiconductor device having high integration degree, enhanced reliability, improved response speed, etc.
The semiconductor device employed in the information processing apparatus usually includes a metal oxide semiconductor field effect transistor (MOSFET) as a unit element thereof. The MOSFET may have a reduced size and high integration degree so that the MOSFET may operate with a high response speed at a considerably low voltage.
To improve the response speed of the MOSFET, the channel of the MOSFET may be formed in a strained silicon layer so that the mobility of electrons or holes in the channel may be enhanced. The strained silicon layer may include silicon atoms having extended bonding length or compressed bonding length.
In a MOSFET including a strained silicon layer, the stress generated in a channel for improving the mobility of electrons may be different from that of the channel for enhancing the mobility of holes. Hence, portions of the silicon layer serving channels of an N-typed MOS (NMOS) transistor and a P-typed MOS (PMOS) transistor may have different stresses than each other when the NMOS and PMOS transistors have increased gate-on currents to thereby improve response speeds thereof. For example, the channel of the NMOS transistor may include tensile silicon along the length of the channel when the NMOS transistor is formed on a single crystalline silicon substrate. Here, the gate-on current of the NMOS transistor may be enhanced because the mobility of the electrons corresponding to the majority carrier of the NMOS transistor may be increased, thereby improving the response speed of the NMOS transistor. Further, when the PMOS transistor is provided on the single crystalline silicon substrate, the channel of the PMOS transistor may include compressed silicon in the length of the channel. In this case, the mobility of the holes corresponding to the majority carrier of the PMOS transistor may be enhanced such that the gate on current of the PMOS transistor may be increased. Thus, the PMOS transistor may have improved response speed. However, the NMOS and the PMOS transistor may not be properly on one silicon substrate as the stress in the channel of the NMOS transistor may be different from the stress in the channel of the PMOS transistor.
To settle above-mentioned difficulties, U.S. patent application publication No. 2005/0136583 describes a transistor having high response speed by adjusting stress in a channel region thereof. According to the U.S. patent application publication, a gate electrode and source/drain regions are formed on a silicon substrate, and a layer having tensile stress is formed on the silicon substrate having the gate electrode and the source/drain regions. Then, a thermal treatment process is performed about the substrate so that a channel region of the transistor has a relatively strong tensile stress.
However, the mobility of holes may be reduced when the channel region of the transistor has a strong tensile stress. Thus, a PMOS transistor may not obtained by the technology described in the above U.S. patent application publication. Consequently, additional processes may be required to be executed for obtaining the PMOS transistor to prevent the channel of the PMOS transistor from having tensile stress when the PMOS transistor and an NMOS transistor are formed on one silicon substrate.